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by akamoonknight
2748 days ago
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I saw the portion of the description that talked about BCD conversion. One magical method I've used in the past on FPGAs is the Double Dabble algorithm [0].
Seems like your implementation is succinct enough to not need improvements, but if you're looking for resource usage reductions it might help out. In addition, always enjoy talking about good ole Double Dabble, such a fun name for an algorithm. [0] https://en.wikipedia.org/wiki/Double_dabble |
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