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That's an excellent question! It's not at all like IP. The basic message size is (IIRC) 64 or 96 bits, comprising a system control word, an application header word, and an optional payload word. The application header word describes what the identity of the sender of the message is (well, in theory it could describe the destination too, but then we'd not have enough space to address much at all) and is used in the routing of the messages. Each chip has a very fast masked CAM (the key IP of SpiNNaker) that is used to convert from the application header word to the destinations to deliver that packet to, which is one channel to each core on the chip and one channel to each direction in the logical triangular mesh in which the chips are connected. The router is very fast indeed, and very low power, so we can generally count on routing a packet right to the opposite side of the machine in a few milliseconds, and I'd have to look up the energy cost of a packet (we've published it, but I forget where). I believe our route planning software takes this delay into account. It also tries to put neurons that communicate with each other close together. For greater delays than that, we also have a delay slot system (for up to 16 simulation timesteps, which is approximately 16ms) in our synapse model, and specialized pseudo-neurons that implement longer delays than that on cores that we set aside for the purpose (and which, because they only handle delays, are much easier to make scale). We do source routing mainly because this was hardware designed from the beginning to do neural simulation; source routing is a natural way to implement (an abstraction of) axons, as each axon is capable of connecting to many different dendrites. This is very much an abstraction of what happens in reality, but it has worked well for us. Also yes, our routing algorithms most definitely do try to limit the amount of traffic going down each communication link. Since communication during execution is pretty predictable (at least statistically) this is far more practical than with IP, where the dominating factors relate far more to being able to manage the network without knowing its total state. |
> specialized pseudo-neurons that implement longer delays than that on cores that we set aside for the purpose (and which, because they only handle delays, are much easier to make scale)
I'm curious to hear more about that, as I don't recall hearing that previously. I'm a dev on the Virtual Brain, another simulator starting to be used in HBP (CDP8), for which we derive tract length info from human diffusion imaging and use it to introduce time delays. These can be up to 256 ms. On the other hand, we're usually running a few hundred neural masses (or some specialized datasets go up to 515k nodes). Are those numbers feasible with your delay-neurons?