[locacorten]

This is byte-addressable persistent memory. They look like DRAM DIMMs and they plug into DIMM slots. You access them using your memory controller and not your storage controller. People sometimes refer to them as non-volatile memory (NVM). Intel used to call it Apache Pass.

They're a nightmare to program because OSes do not have a good abstraction for them (at least not yet). Accessing them through the file-system seems sub-optimal (this is byte-addressable memory and not a block device). Accessing them through virtual memory is also pretty bad because they're much slower than DRAM.

[pbalcer]

Disclaimer: I work at Intel on PMDK (pmem.io)

Both Windows and Linux implement DAX, which, as @the8472 explained, allows bypassing page cache in memory mapped I/O. Additionally, DAX optionally allows you to flush your data directly from user-space instead of calling msync.

And that's the gist of NVM programming model [0], its entire point is to allow applications to avoid the now hugely excessive abstraction layer of traditional storage.

And I will freely admit that programming to raw memory mapped files can be difficult, but there is ongoing work on making it easier. An example of that is, excuse the shameless plug, Persistent Memory Development Kit [1], which makes writing new software for this new type of memory much simpler.

Performance of an NVDIMM is obviously hardware dependent, but the now widely accepted programming model works with the assumption that persistent memory is fast enough so that it is reasonable to stall a CPU while an instruction is accessing it. I'm not sure on what hardware evaluations you are basing your claims on, but let me assure you that the HW solution being described in the blog post does not violate that assumption.

[0] - https://www.snia.org/tech_activities/standards/curr_standard...

[1] - http://pmem.io/

[simcop2387]

Do you know how well tools like Cap'n Proto and Protocol Buffers help for dealing with this kind of scenario? I'd imagine that some kind of low latency/cost serialization system would help significantly in using the device. Cap'n Proto I'd imagine would work nicely for reading data off since it should be able to read and use the structure with no extra copying or decoding, but I have no idea how the situation with writing would win out.

[pbalcer]

That's an excellent question. The answer is that those type of libraries will work just fine for read-only workloads since you cannot mutate a data structure once you have serialized and written it out to a file. The best part is, this will work without any (or very little) modifications, as long as your application is suited for using mmap. All you have to do is to use a persistent memory resident file on a DAX file system.

If you need dynamic mutable state however, as great as these libraries are, you will need a more complex solution with memory allocation and transactions.

[wtallis]

The simplest way of using this is to not do any serialization at all, just store any information you want persisted in memory allocated from the region you mmaped to the Optane DIMMs instead of the DRAM DIMMs.

[simcop2387]

The main reason I've been thinking about tools like that is more because the persistent structure should probably work regardless of compiler settings/flags and code updates. Directly mmaping the structures you're going to have to worry about how things are packed, and if a new compiler optimization causes things to go differently (something gets eliminated in one version and not the other).

[derefr]

I would say that this is still a mentality of thinking of something as "data on disk", where the data should be in an "ABI-stable" format.

Think of persistent-memory data as more like data resident in the memory of a runtime which can experience a "hot code upgrade", like the Erlang runtime.

In Erlang, when you hot-upgrade your running code, you usually do so through a managed system of "relups" (RELease UPdates), which are sort of a cross between an RDBMS migration, and a traditional installer-package full of newer versions of code and assets.

The Erlang runtime takes this package, unpacks it, and then runs a master relup script, which can been authored to do arbitrary things (including, if ultimately necessary, fully rebooting the node, throwing away all that in-memory state.) Mostly, though, a relup script calls into individual "appup" scripts for each Erlang application. Those applications then specify how their corresponding running processes are to be updated—which can sometimes be fraught (if e.g. the new release requires that you add new service-processes or remove old ones, migrating in-memory state into a new architecture), but usually just means calling a "code_change" callback on all the service-processes.

This "code_change" callback is the thing that's most like an RDBMS migration: it is called from the event-loop running in the old version of the code of the service-process, and passes in the old in-memory state; and when it returns, it's returning the new in-memory state, to resume the event loop in the new version of the code of the service-process.

This is basically how I'd picture dealing with code updates (including ones due to build-setting changes) in software that deals with pmem: you'd architect your code such that the library that touches the pmem can have multiple versions of it dynamically loaded (though not running) at the same time; and then you'd stage a migration from the old code's pmem state encoding, to the new version's, by

1. dlopen(2)ing the new version of the lib;

2. telling the old version of the lib to stop any ongoing work;

3. handing off the toplevel pmem state-handle that the old version of the lib was using, to a "migrate" function in the new version of the lib;

4. replacing the old version's pmem state-handle with a dummy one;

5. telling the old version of the lib to terminate (and so do the trivial cleanup to the world it sees through the dummy handle);

6. tell the new version of the lib to initialize, using the handle to the now-migrated-in-format pmem;

7. dlclose(2) the old version of the lib.

Basically, picture what something like Photoshop would have to do to enable you to upgrade its plugins without restarting it or closing your working document, and you'll have the right architecture.

[wmf]

So does that update process rewrite all 6 TB of data in the new format? Because I can imagine why people would rather not do that.

[puzzle]

Probably something like Flatbuffers, with which you can skip the marshalling and unmarshalling. It was designed for games, where you would map files into memory.

[wmf]

The ultimate zero-cost serialization system is just mmapping the Optane and casting pointers, but if you want something less fragile you could probably use one of those libraries on top of mmap.

[the8472]

> They're a nightmare to program because OSes do not have a good abstraction for them (at least not yet).

With DAX[0] linux already has the ability to put a filesystem (currently ext4 and xfs) on NVDIMMS and then let userspace address them through mmap while skipping the page cache indirection. I.e. you're directly byte-addressing them through the memory controller via standard memory-mapped file abstractions. Direct block device mapping of nvdimms without filesystem is also possible.

[0] https://www.kernel.org/doc/Documentation/filesystems/dax.txt

[markdoubleyou]

The Persistent Memory Development Kit (PMDK) offers high-level abstractions over DAX. Looks like most mortals would use libpmemobj (or its C++ bindings).

http://pmem.io/pmdk/

[Symmetry]

It seems like Single-level store[1] would be a really good fit for this. I was going to make a crack about bringing back Multics but apparently IBM has an OS using this.

[1]https://en.wikipedia.org/wiki/Single-level_store

[devit]

Is there are a reason to not just use DRAM along with a battery to achieve the same persistence but as fast as DRAM?

[juancampa]

Probably because systems that passively do their job tend to be preferred.

Also a battery would only last so long. IIRC DRAM needs to be constantly refreshed, so, it would be a trade-off between capacity and duration.

Optane seems[1] to be 20~30X slower than DRAM but 4~10X faster than server SSDs

[1]: https://superuser.com/a/1195674/187732

[wtallis]

There are NVDIMMs that have DRAM and a matching quantity of NAND flash memory to save the contents to in the event of a power failure. They require an external capacitor module and are limited in data capacity by how much DRAM you can fit on the module. You can fit far more 3D XPoint memory on a module than DRAM, and it doesn't require the external capacitors to achieve persistence, and it should be significantly cheaper on a per-GB basis.

[cdoxsey]

Just to reiterate the point... this is an instance with terabytes of near-memory-speed storage.

If persistent memory pans out as a technology it will completely upend the way we think about building software and the cost tradeoffs of hardware. (as much as or more so than the transition from spinning disks to ssds)

[Dylan16807]

How do you define "pans out"? What performance and price differences between it, flash, and DRAM do you have in mind?

Because I'll keep reminding people that putting a DRAM cache in front of some flash can very closely approximate a large persistent memory. If people wanted to build software for that kind of system, they could do it today. The hardware is not the blocker.

[wmf]

Diablo Memory1 used flash DIMMs with DRAM DIMMs as cache. When we tried it, it worked OK for some workloads and poorly for others, but it was also buggy and then the company went out of business. So a large part of "pans out" is simply a production-quality implementation that you can buy.

Note that Optane DIMMs have been delayed by around two years at this point and we still don't know what they will cost.

[SergeAx]

Cache will always stay just cache, unless it is the same size that an underlying persistent storage. You cannot read or write larger-than-cache chunks without performance degradation. Also you have a start-up cache-warming problem.

[Dylan16807]

Most workloads don't need the entire storage to be at maximum speed all the time. In other words, in most situations cache is plenty for speed purposes. And the mapping layer can hide the chunk sizes. But we still don't see people writing software based around persistence. Maybe a lot of people are simply stuck in their ways, or maybe the benefits aren't actually that big.

As for cache-warming, that's also a configuration issue. When you reboot, leave the 'cache' portion of DRAM alone. Then as soon as the service resumes, the cache is already hot. When you shut down a node for an extended period, consider spending five minutes writing the cache to disc. And the article is about cloud servers anyway, where a shutdown typically implies losing all local storage whether it's persistent or not.

[manigandham]

The reason is the battery. These devices can be powered off and save state, like an SSD.

[piotrkaminski]

But in the context of the OP, presumably devices in a data center would never be powered down on purpose to save energy? In which case it seems that battery-backup DRAM would work just as well for this use case, and be both cheaper and faster.

[jordanthoms]

Optane is in between DRAM and flash in terms of cost (and performance) - it's also denser, so you can fit much more storage on each DIMM slot.

[zokier]

DRAM can not be simply naively battery-backed; it needs active refreshing. And as memory controllers reside in CPUs these days, that would mean keeping the CPU powered up.