[olliej]

The traditional (eg mips) definition of risc was that the cpu should not hide how it operated - in essence, the compiler was required to schedule operations efficiently itself for both performance and correctness. That’s why MIPS and others have things like branch delay slots. It turns out that that is a terrible idea - it means binaries are tied to a specific micro architecture, let alone a separate implementation of the same ISA. Traditional risc also did not support floating point or integer division (both in software), except again software is necessarily slower than a hardware pipeline.

So risc has slowly become analogous to “more registers, orthogonal instruction set, not x86”