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by zipcpu 2820 days ago
The specification actually mentions RISC-V, and why I didn't use it. In hind sight, it's harder to decode the RISC-V instruction set than the one for the ZipCPU--to many holes in strange places.
1 comments
scottlamb 2820 days ago
Where does it mention RISC-V? I'm curious to read it. I hit ctrl-F to search for RISC-V in https://github.com/ZipCPU/zipcpu/blob/master/doc/spec.pdf and only found a brief mention under "2.2.7: Operand B".
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zipcpu 2820 days ago
Check out page ix in the preface.
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