[henrikeh]

This is one of the most actively researched fields in computer architecture/engineering. Hard real-time requirements has been been extensively researched for ISAs, compilers, network-on-chips, concurrency models etc etc.

Personally, I was briefly involved in the T-CREST[0] project where a complete ISA, network on a chip and compiler where devolved in tandem to support deterministic timing and well understood worst case execution times (WCET).

As an example, the ISA explicitly defines multiple caches with different write-rules. So for example the stack cache is write-back to lower WCET.

The whole project is available as a VM image[1] where the HDL can be compiled to an emulator and/or synthesized to hardware.

[0]: http://www.t-crest.org/page/overview [1]: http://patmos.compute.dtu.dk