[snops]

Moore's law will take care of the processing cost nicely, especially as more commodity processors become powerful enough to handle it.

The ADCs and other analog stuff might be more of a hurdle, the design of them is quite hard, they aren't able to take advantages of smaller transistors as well, and competition in the space is decreasing as semiconductor companies keep merging (e.g. Analog Devices and Linear Technologies).

[namibj]

At these low frequencies very simple oversampling Delta-Sigma ADCs work well, considering the sample rate is in the low 3-digit MHz range at most, which can easily be processed by even an 15$ FPGA that has SerDes suitable for USB3 or PCIe2 [0]. Considering you can just shift the noise out of the frequency of your ultrasound with the correct averaging filter in the FPGA to convert the 1-bit high sample rate to many-bit passband (one might want to fold the quadrature demodulator for RX phase sensitivity into this filter to save on comnpute). It would basically be a many-channel, fixed frequency (by software configuration only) RX SDR.

[0]: https://www.mouser.de/ProductDetail/Lattice/LFE5UM5G-25F-8MG...

[madengr]

The clock jitter may get you. You can oversample and decimate to obtain the equivalent ENOB, but then the sample clock stability becomes more difficult and costly.