[akuma73]

Sorry to burst any bubbles here, but this is s very incomplete implementation.

You couldn’t run anything but small toy programs on this machine. This is more like what a student would build in an undergraduate course in computer architecture.

For example, there is no MMU, no debug support, no traps, no interrupts, no exception handling, no OS privledge levels, no FP, no memory controller etc.

Of course, one wouldn’t implement all of these in a few hours.

The fact that this is RISCV is somewhat of a red herring as you could do a similar thing with a restricted subset of MIPS or ARM or even x86 as they do in UT Austin’s comp arch class.

[samsoniuk]

I fully agree with you about the missing features! However, as long my objective is replace some legacy 680x0/683xx/coldfire processors running small toy programs, I see no need for that complex features. Please keep in mind that although 25% of RV32I instruction set is missing in my implementation, there is no side effect, since that instructions are not relevant for this specific environment (fencex, exxx and csrxxx), since the gcc generates by default exactly the implemented subset and nothing more. I think this is a very important advantage in the RISCV architecture when compared with others and I dont think the gcc will have the same benevolent behaviour in the case of ARM or x86. Maybe for MIPS is possible, but I am not sure about it. Anyway, why not use RISC-V? :)

[jonjacky]

Yes. Part of the motivation for RISC-V was to enable designers to do one-off experiments like this or small production runs with custom ISAs based on RISC-V, without having to worry about licenses or intellectual property issues. RISC-V even leaves some op codes uncommitted so designers can add their own custom instructions. Dave Patterson (RISC-V designer and Turing award winner) explained this at a talk I attended a few years ago.

[aappleby]

An Arduino has none of the missing parts you mention (except interrupts), yet it's quite a useful device even in non-toy applications.

[akuma73]

The cortex m0/m3 CPUs most certainly do have breakpoints, svc (trap), interrupts and an optional memory protection unit.

The Atmel CPU is more constrained but still has hardware breakpoints, IO instructions, watchdog timers and interrupt support. It also has far more complex addressing modes (more CISC-y) to save on instruction counts and a variable length instruction set encoding where memory space to store code is a first order concern.

I’m also sure there is a memory controller to control the SRAM.

So, even if you were to build a simple micro controller, you’d need a lot more features and most likely higher performance (and power efficiency) than you would get from a trivial 2-stage pipeline. Not to mention there are no instruction or data caches in this RISC-V machine.

[samsoniuk]

Good point, but unfortunately the focus of the project is only the RISC-V core running in a FPGA. Everything else is already widely available in the internet and can be easily integrated.

[hesdeadjim]

That class was one of my favorites at UT. I was lucky enough to have a guy from Intel teach it as an adjunct.

[amelius]

What book did you use?

[hesdeadjim]

It’s been about 14 years so not entirely sure. The textbook was using a RISC architecture from what I remember. We also had a semester long project where we had to research and invent a new x86 instruction to speed up a program of our choice. It was... intense.

[AboutTheWhisles]

You have pretty high expectations for one night of work