[mikeymop]

What about building up? It seems most designs are relatively two dimensional.

AMD's High Bandwidth memory and Samsungs high density NAND seem to open up another axis to continue doubling transistor count in a given area.

It'd be interesting to see things be engineered this way as devices are starting to become too thin to be comfortable.

[MrEldritch]

The fundamental problem with three-dimensional logic is heat. Getting the heat out of the chips so they don't melt is already one of the largest performance bottlenecks in the entire industry; putting more layers on top where they block heat flow out of the interior layers makes the cooling problem intractable.

3D memory is a lot more tractable because it doesn't have to do nearly as much as a CPU. You don't typically worry about cooling your RAM.

There is a type of logic efficient enough that we can think seriously about monolithic 3D integration; superconducting Josephson junctions at liquid-helium temperatures are really, really efficient. There's some hopes that spintronics may one day give us sufficiently efficient switches at room temperature.

But we've wanted to integrate our chips in 3D for decades - transistor scaling aside, routing latency adds a lot of overhead and the length of the wires you need only gets worse the more transistors you need to connect with them. (It's an n^2.something scaling, IIRC). All else being equal, 3D integration of the exact same number of transistors as a 2D CPU would result in a major performance boost all on its own, by making the routing much more straightforward and direct.

The reason we haven't done it isn't because we haven't thought of it, or haven't tried to do it - it's because we can't. (Also, manufacturing a 3D chip is really tricky)

[marcosdumay]

The largest practical problem with going 3D is how do you cool the chip?

But then, what is really the gain? You will be trading a larger number of chips per die for a proportionally more expensive process. Besides some faster communication (may be great for L1 cache), I can only see it adding problems.