[jl2718]

Here’s something. Rad-hardened parts are mostly BS. An MSP430 takes 20krads without shielding. Process shrink seems to increase hardness, not decrease. I used flash FPGAs with parity circuits because flash was supposed to be better for SEU. This is all theory; it’s really hard to test SEUs. Store firmware as a low-rate RS and do circuit parity checks to trigger firmware refresh. There is probably a smarter way to do circuit ECC without the EC as a weakness, but I don’t know. That was years ago, and we were just space cowboys giving the middle finger to the rad-hard parts business.