[irq-1]

Here's an interesting paper that discusses some design issues.

https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7086415

> To mask the effects of upsets in the FPGA configuration memory, temporal or structural redundancy can be applied to the system. Temporal redundancy involves the replication of a computation or logic function in time to mitigate failures that occur during one of the redundant computations. Structural redundancy involves the replication of selected circuit structures to remove single-point failures. Failures in the circuit can be masked by performing the logic or computing function in more than one circuit location.

> The most common form of structural redundancy is to apply triple-modular redundancy (TMR) [24]. As shown in Fig. 6, TMR involves the triplication of all circuit resources and the addition of majority voters at the appropriate circuit outputs.