[mikepurvis]

I think the main issues are that it would be crazy slow, and flash isn't really random access for write— you still have to blank whole pages at a time, so you'd definitely still want a RAM caching layer in front of the flash, even if it was being synced on a second by second basis.

Plus the whole wear levelling thing would have a huge impact on lifespan.

Tiny microcontrollers would be the first ones to benefit from an all-flash architecture, but they all still ship with both flash and RAM onboard.

[dfox]

NAND flash isn't random access even for reading, but generally these limitations are not inherent in the technology, but are motivated by reducing the die area per bit of storage (and thus cost). Purely random access "Flash" is typically called EEPROM and readily available with SRAM-compatible interface (and costs several times more than SRAM).

In the microcontroller space there is for example TI's MSP430FR series which has unified non-volatile storage based on what could be described as core-memory on chip.