[jdoege]

What I have negative to say has more to do with those producing implementations than the architecture or RTL. In order to have the security afforded by being open, every part of the process must be open from the spec to the silicon. The entities producing RISC-V devices are simply passing forward the RTL along with their additions and changes. They are not releasing the work product of any of the steps between there and silicon. There are many differences between RTL and the gate-level representation, many of which represent potential security issues (testability features, for instance.) Between gates and physical design more changes can be made and between physical design and mask, even more. Some of those could result in sloppy security holes or some could even be maliciously introduced security holes. With any of the current providers there is no way to know or test for these potential issues.