[nerpderp83]

> And the innovation never comes from the chip companies, it comes from companies that are building the products.

I agree with you.

Eng has really got to stop thinking they are the source of ideas, most good ideas come from customers that have needs that can't be currently met. Eng balances design constraints, as companies grow, hierarchies get stronger and creativity drops. Maximum innovation comes from small companies solving customer (the ones building the products) problems.

The Jelly Bean chip business could get disrupted by the proper mix of analog and digital. The PSoC [1] was almost but not quite there

[1] https://en.wikipedia.org/wiki/PSoC

[ChuckMcM]

I think you are correct as well, its a matter of timing. Eventually there will be the equivalent of an FPGA that instead of having "LUT"s or "CLB"s they will have a bunch of useful bits of tech and an internal wiring bus that will be programmed by setting switches or blowing fuses. Then the variation will be how many pins on the package which will determine how many of these things you can bring out to pins.

I did a thought experiement of what it would take to make a 'universal' TTL chip, which was basically a 14 pin, 16 pin, and 18 pin device where all 74xx chips were actually inside of them and through a programming step you bonded one of them to pins on the lead frame. It required a 90nm or better feature size. The trick was you only have (number of pins) number of input stages and output stages (all the "TTL" part of TTL (these are fairly large by their nature). The logic was all internal 1.8v with a simple step down regulator to go from 5V down to 1.8V.

You could cover both the SSI and MSI catalogs. Of course there isn't anyone designing new stuff with TTL any more so it remains a thought experiment only.

[nerpderp83]

This would have been a godsend for managing inventory.

In a somewhat related idea, is that of unioning the footprint of alternate parts in a PCB design so that either part could be used. I have never used any high in EDA software, but if you had end to end design, schematic, pcb layout and parts databases with high level machine-readable symbolic pin descriptions, these could be inferred automatically (unioned footprints).

Using your idea, I wonder if you could automatically have "hot standby" components in the same package?

[skybrian]

Based on a link posted not long ago, FPGA's seem to already be changing this way:

http://semiengineering.com/fpgas-becoming-more-soc-like/