That's true. 3D won't help with processors as much, because of heat dissipation issues, but storage will benefit.
However, the planar silicon scaling is what primarily enables cost reduction for production. I expect the (total device) density to continue to increase with the 3D tech, but cost will go up with capacity increases. Maybe not linearly though, because you don't have to pay for extra packaging.
I would not rule out 3D from processors yet. Such an invention would be able to reduce die size and likely cost. Heat density is probably the real problem and may need some additional inventions.
The 3D memories will probably see some planar (x-y) scaling, they just don't need all of their scaling from it. 3D scaling will still increase bits/die area, and thus reduce $/bit. If doubling the stacking height doubles capacity but adds 30% to wafer cost with extra processing steps, its still much more efficient than 100% cost for two wafers of the previous design.
Scaling efficiency shouldn't be too dissimilar from planar scaling, at least until the next wall is hit.
However, the planar silicon scaling is what primarily enables cost reduction for production. I expect the (total device) density to continue to increase with the 3D tech, but cost will go up with capacity increases. Maybe not linearly though, because you don't have to pay for extra packaging.