| I had to register to comment about TI "quality" and friendliness ;-). Their SoCs are ridden with HW bugs and TI will not put every HW bug to errata - e.g. their infrastructure pktdma will hang if you will use chained descriptors but you will not find it in silicon errata. TI response was - "just don't use it" and refused to verify it on their side. The ISA of c66x DSP is just stupid - you have quad SP multiply but only double SP addition - forming registers back and forth in quads will result in MV instructions often (because compiler is not so smart).
There are no real vector registers, "vector" instructions take 4 or 2 32bit registers. Want to compute power of individual complex int16 in a vector ? You are out of luck - DDOTP4H will add everything together. There is even no way to utilize their multipliers fully since load&store is 2x64 bit, while multiplier can perform 8 SP multiplies per cycle. Moreover memory access to L2 is so slow that you will wait in memory stalls (there is no HW prefetch from L2 to L1D cache) and L1 SRAM is way to small to do anything serious (32 kB). After trying other DSPs, like CevaXC or VSPA, TI looks like poor joke. Their C7000 that supposed to address some of those problems is long overdue and will be well underpowered comparing to recent Ceva DSPs or NXP VSPA. |