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by kirvyteo 2948 days ago
I am the co-founder of Plunify. We have an ML software solution (InTime) that optimizes FPGA design by tuning the parameters of the compilation, i.e. synthesis, P&R. I don't know much about memcached accelerators but if it is a performance driven application, like HFT, I believe we can make it go even faster, i.e. increase the FMax. I read from your website that you are using Intel PSG devices. We often see designers using seeds to close timing or optimize the timing, but that is leaving performance on the table. For more details: https://support.plunify.com/en/2018/04/17/compare-timing-per...

Happy to talk more at kirvy@plunify.com if you are interested. Congrats on getting a seed round from Intel Capital!
1 comments
andrewcanis 2948 days ago
Interesting, what synthesis settings have you found have the most impact? I have also seen FPGA designers trying different seeds when closing timing. In this case, AWS provides an FPGA shell for external interfaces that has a maximum clock frequency of 250MHz. We have been able to meet this timing constraint without many issues. But we will keep you in mind for the Intel FPGA boards we are working with now.
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kirvyteo 2948 days ago
what synthesis settings have you found have the most impact?

The answer is - it depends. Unfortunately, we have not found a "golden" combination of settings yet. If you have a highly congested design, synthesis does help a lot, but not all cases. There are correlations between the settings, so if A is good, B is good, A+B could be bad. Seeds belong to a category of techniques that we classify as random. For example, for Vivado, although Xilinx removed the seeds feature, we created a technique to trigger randomness in the placement using a property of Vivado.

What we do is not new in the sense that settings exploration has always been around. But with cloud compute resources and ML approaches, it really enables timing closure and optimization methods in a cheaper and more disciplined fashion.

We are also very interested in users of OpenCL/HLS/C. The translated RTL is often not as optimized/readable as what an RTL designer will do if he/she does it directly in RTL. Our tool (InTime) can be a good boost to the performance of such RTL.

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