| > You do at least get rid of the Lovecraftian clock distribution tree that's getting problematic for current synchronous logic. No, you don't. You make it even bigger and far more complex. You can take any synchronous design, and refine the clock gating further and further, to the point where no part of it gets a clock transition unless it actually needs it on that cycle. And then when you're finished, congratulations, you've made an asynchronous circuit. Fully asynchronous design and perfect clock gating are one and the same thing. The clock distribution and gating approaches we already have are actually a sign of progress towards asynchronous design; they're just quite coarse-grained. Of course, it's probably not the case that a clock-gating transform of an conventional synchronous design is also the best possible solution to a problem, so there's clearly still scope for improvement. But a lot of the possible improvements are probably equally applicable, or have equivalents in, optimising clock distribution and gating in synchronous design - because that's ultimately the same thing as moving towards asynchronicity. So talking about clock distribution issues as a problem that will just go away with asynchronous design is misleading. |