[28mm]

I am confused by this—-aren’t ASICs the costliest option until some (high) number are fabricated and put into use?

If FPGAs can implement these changes efficiently—more efficiently than cpu miners—-and be re-synthesized to implement further changes, doesn’t that advantage them?

[ethbro]

Parent was presumably leaving unsaid "... at scale", aka enough to move a chunk of the hash power.

[stevedc3]

Thanks yes I totally meant scale. Main cost of new ASIC chips is design and fabrication. Only serve a very narrow specific purpose and all that cost is sunk. But after that, unit production chip cost is negligible.

[arthurcolle]

do you happen to know b/e costs given difficulty/profitability ratio using current market electricity prices?

[QML]

"How would you decide when to use an FPGA and when to create an ASIC? That depends. FPGAs waste a large amount of silicon compared with an ASIC, so the cost floor, which depends in large part of the surface area of silicon required for the chip, is often an order of magnitude higher than you’d want it to be. But fabricating an ASIC isn’t cheap either."

[1] https://spectrum.ieee.org/tech-talk/computing/hardware/lowbu...

[tfha]

ASICs are only costly from an R&D perspective. Which means once someone has all the R&D, they can be a monopoly and get really cheap hashrate, and since they are an incumbent monopoly it's much harder for another company to step in and complete.

FPGAs don't suffer this problem

[dragontamer]

I mean, a serious FPGA lab would simply keep their FPGA techniques secret until they build a sizable advantage. There's a lot of tech that would be built up: a custom memory controller, an implementation of various Cryptocoin PoW systems, and of course, the Bill of Materials for the ideal power-efficiency for various designs, etc. etc.

Something like an FPGA + Interposer to HMC would be a huge R&D effort, and just as centralizing.

BTW: None of the designs I've talked about are strictly speaking commodity. They'd require at a minimum, custom PCBs. Maybe more advanced techniques for the best technology (again: Custom Interposer to HMC + FPGA interface + all the Verilog / VHDL code to make it happen).

As long as an FPGA-based shop kept their FPGA PCB secret, as well as their code secret, and their Device Drivers secret (You'd probably run Linux / Windows to talk to the FPGA over PCIe) then they're basically going to be ahead of the rest of the competition. Eventually, the competition would catch up, but a constant R&D effort into newer designs (ie: testing HBM2 vs HMC vs RLDRAM3 vs QDRIV, building relationships with suppliers, etc. etc.) could lead into a sustainable business edge.

Heck, early on in Monero's life, some dude got to like 40%+ of the entire network's Hash Rate by simply writing better CPU code and keeping it for himself, and then spending hundreds-of-thousands of dollars on AWS: https://da-data.blogspot.com/2014/08/minting-money-with-mone...

> By the 14th of May, we were 45% of the total hashing power on the coin. Things started to get a little exciting

FPGAs would be that on steroids. There are way fewer Verilog / FPGA engineers. It also would require custom PCBs and hardware engineers to make it all happen. I wouldn't even know who to ask to design an Hybrid Memory Cube interposer and to fit it on an FPGA for example.

[krupan]

A quick google search turns up at least one devboard with a beefy FPGA and HMC:

https://www.xilinx.com/products/boards-and-kits/dk-u1-vcu110...

Not cheap, and probably not available in bulk, but cheaper than custom PCB R&D.

[dragontamer]

Not cheap, but it would be insane for cryptomining purposes if you somehow got a sizable supply.

16.5 MB of internal RAM. 18MB of QDR-IV SRAM. 125MB of RLDRAM 3. 2GB of HMC.

That's plenty of RAM to pretty much crush Ethash, Cryptonight and more.