[qubex]

I’m curious to know what leads you to consider the RISC-V to be a “workstation-class CPU”. As I understand it’s an ISA that aims to be pretty broad, and is expected to compete (at least initially) with low-end embedded MIPS chips that are pretty ubiquitous everywhere in all sorts of devices.

[garmaine]

I’m talking about U54 from SiFive specifically.

[opencl]

The U54 is squarely in the Pi competitor category. Claimed IPC is slightly lower at 1.7DMIPS/Mhz vs 2.3 for the Cortex-A53 in the Pi and this SoC clocks slightly higher than the Pi at 1.5Ghz vs 1.2Ghz, so performance should be quite similar. I certainly hope it manages to catch on and we get higher performance RISC-V chips at a reasonable cost in the future but these are clearly not it. If by "workstation class" you mean Skylake/Zen levels of performance there's a long way to go.

[jabl]

The U54 is a single-issue in-order core. Again, what makes you label that a "workstation-class core"?

[garmaine]

The company's stated plans for the product line.

[qubex]

Well... this certainly isn’t workstation-class performance. This is more like a smartphone SoC.

[jabl]

Hmm, my google-fu seems to be failing me, do you have a link where the company states that?

[garmaine]

No, I’ve learned about SiFive from the talks they’ve given at the RISC-V workshops. I think some of those are recorded, maybe look there? I’m on mobile and it’s hard to provide a link.