RISC-V is a open specification (actually a couple of them) backed by a the RISC-V foudnation, which "anyone" can use to implement a design on their own.
So they are closer to what ARM is, which licenses IP for others to implement.
To put that into perspective, reports I read put MIPS at $700-900k with ARM starting at $1+ million. Buyers of those get their ecosystem of existing tools, OS's, libraries, etc. RISC-V doesn't have much of an ecosystem yet. However, if FOSS software covers application requirements, then a SOC using the RISC-V chip saves a lot of money upfront. Even more down the line since SiFive doesn't charge royalties.
(Edited to change part about royalties after reading article more closely.)
From what I understand, the RTL of these cores and a good chunk of the stuff around them is open [1]. The cores themselves are basically all specialized Rocket cores. What you're paying for is probably the ready-to-fab routed cores in whatever CAD format and support.
They charge for the peripheral IP and system design. The actual computation core architectures are freely available on GitHub under open source license.
You seem to be confused about the terminology. A typical CPU core is an ASIC.
An ASIC (application specific integrated circuit) is exactly what it says on the tin - an integrated circuit designed to perform one function - in this case, executing machine code. Most of the chips you see inside electronics are ASICs (everything from operational amplifiers to ethernet PHYs and CPUs).
I don't usually see the two terms used together, because of the "application specific" vs "general purpose" thing. So I thought there might be something I was missing.
So they are closer to what ARM is, which licenses IP for others to implement.