[phkahler]

Have a look at slide 43 here:

https://riscv.org/wp-content/uploads/2016/01/Wed1345-RISCV-W...

This is from a couple years ago. Even more important (I can't find it right now) is that risc-v compiles code to fewer bytes than x86 and fewer micro-ops as well. With the smaller/simpler instruction set it also requires less area and power, so it may be just a matter of time now.

[jabl]

I guess the "even more important" thing you're thinking of is https://arxiv.org/abs/1607.02318 ?

So with RISC-V GC + macro fusion of a few common idioms you get slightly less micro-ops than x86-64, armv7, or armv8.

That being said, for high-performance cores such as Skylake, POWER9, or the latest aarch64 server cores the ISA probably doesn't matter that much.

[phkahler]

Yes, that what I meant. But the small number of instructions on risc-v means less hardware to implement it. If it wins on code size and micro-ops but has far fewer instructions to deal with, it should result in smaller circuitry to implement. So far it has been implemented with less area and power consumption than ARM cores of similar performance and there doesn't seem to be a reason it can't scale to bigger/faster cores the same way x86 has.

[jabl]

I think the usual argument is that the decoder is a small fraction of the total transistor count in a high-performance core.

For microcontroller class HW, the x86 ISA might be a crippling disadvantage compared to RISC-V. For a high-performance core, which AFAIK is something like 20-30 million transistors, not so much. The bigger the core, the smaller the advantage of the ISA.

But yes, I don't there is any reason why RISC-V couldn't be used to create a high-performance core competitive with the x86, POWER, ARM of the day. It's just a hugely expensive affair.