[throwawaysml]

> Your other comment about NFLX makes you seem suspiciously and hilariously like a sock-puppet account so I can't actually be candid on that now.

I really wondered why they didn't mention POWER at all two weeks ago in the blog post. And now this post allowed me to raise the question. I'm curious what you think I represent for me to be a sock-puppet.

I cannot prove it, obviously, but this is just a throwaway account of a single person who doesn't represent anyone and definitely isn't paid to participate on Hacker News. Neither am I employed by any large or well-known organization to have some kind of intent. I'm just a programmer who wishes we had more POWER machines just like Raptor is trying to achieve.

I did feel uncomfortable asking the question as it might be obtrusive and thought I managed to word it defensively enough. Sorry, looks like I failed :).

> For getting vendors to do things, it helps that I have a 8-figure HW spend.

Thanks for answering!

That's encouraging to hear, although sounds like I would need to be the operator of a video hosting or cdn network or HPC cluster before I could request a consultation with engineering executives. I'm most excited you have good relations with Chelsio since I love their NICs and FreeBSD drivers. I couldn't care less about Intel NICs tbh.

[kev009]

Mainly because I have been trying to sign them up with similar reasoning. A lot of people spent foolish amounts of capital on arm64 enablement, I'm glad FreeBSD has it for embeded stuff, but the server-class silicon just sucks compared to intel, amd, and P9. Follow along and watch in 2018 :)

[throwawaysml]

Hah, I never understood the appeal of AARCH64 either. It's not like it's some super clean ISA or that they won't run into similar power-vs-IPC conumdrums when they start to create x86 competitive server CPUs.

I've always been fascinated by the ARM and PPC embedded support on FreeBSD, which reflects the real market and not some fantasy land. Which also explains the sad state of the POWER port right now.

I'm fairly certain that RISC-V will eat ARM and it already started on the bottom end with embedded chips being replaced with RISC-V. nVidia, storage (SSD, HDD) vendors already have RISC-V silicon deeply embedded, hidden in sight. I feel like it will be the FOSS "revolution" all over and more progress because there's no need to pay stupendous amounts of licensing fees to ARM Inc. One could have done this with OpenSPARC too, but for political reasons or technical limitations of the ISA, it never took off.

My prediction is that many embedded ARM chips will be replaced by RISC-V. It won't be free because someone has to create the desired chip IP, unless you're happy with the free ones, but there will be competition that doesn't involve a parent licensing agency grabbing all the money for an ISA they invented 30 years ago. Good times to be a compiler codegen developer :).

[carterschonwald]

Woah: there’s little risc v’s in wide spread heardware hidden in plain sight?

[throwawaysml]

These things are very hard to find concrete data about for outsider, which I am one of, but at least nVidia has published that they're building their new Falcon controller chips based on a custom RISC-V architecture. It's hard to tell how widespread it is since they are not buying chips from Renesas or MIPS and looking at the board wouldn't necessarily show you there's a RISC-V chip in there. All we need now is a high performance variant of lowRISC to combine it with its safety features, port seL4 and MirageOS to it. Then would get finally get back what we had with the old Burroughs machines and enjoy safety and performance without having to choose.

Anyway, they announced this publicly in 2016 so I assume it's already hidden in some nVidia hardware. I also read about a storage vendor (Seagate? or WD?) working on a transition to RISC-V, but I cannot find it right now.

https://riscv.org/wp-content/uploads/2016/07/Tue1100_Nvidia_...

The reasons cited sound like those we heard about Linux and Samba or Linux and Apache in the past.