[jleahy]

You can actually get an ASIC manufactured for a few thousand dollars via CMP or Europractice. So not quite Google money. The difficulty is in paying for the software licenses you need to go from Verilog to DRC checked GDSII files (which is what you need to send to them).

In fact personally I think this is a much better route for open source hardware. Reverse engineering FPGA bitstreams impressive, but you're swimming against the tide. If we had good open source tooling for synthesis/place-and-route/DRC checking and good open source standard cell libraries (and these things exist, eg. qflow, they're just not amazing currently) then truly open source hardware could actually be a thing. Even on 10 year old fabs you'll get much better than you could do on an FPGA (you just have to get it right first time).

[cottonseed]

There's also efabless: https://efabless.com/

Europractice has prices online: http://www.europractice-ic.com/general_runschedule.php

[deepnotderp]

MOSIS is also an option in the US, albeit more geared towards industry.

[exikyut]

I'm very interested in this. I read that one small design (which I knew was very small, but not quantitatively so) cost approximately $5k per small run.

How is the cost calculated? I presume size of final wafer (ie, number of chips produced) at least; does transistor count per chip influence anything too?

Finally, is it possible to produce and maintain a fully open-source design that's the chip-fab equivalent of the book publishing industry's "camera-ready copy"? I get the idea that this is specifically where things aren't 100% yet, but, using entirely open tools, can you make something that is usable?

[jleahy]

The cost depends on the technology. More modern processes are dramatically more expensive (don't even think about something like 28nm). If you're looking at something ancient like 130nm, 0.35um, etc then it's going to be something like $1-2k per mm^2. Normally there's a minimum cost of a few mm^2. Expect to get a few tens of chips back. Transistor count has no effect, they couldn't care less what you put inside your part of the wafer, so long as it follows the design rules (for example minimum % coverage on each layer to prevent it collapsing vertically), but obviously if you need more transistors you might need more area.

Yes it's 100% possible to do an open-source design, qflow has been used to make sub-circuits of ASICs, but it's going to be extremely difficult. There are lots of things missing which you'd have to take from the fabs PDK or design yourself, for example open source I/O pads (sounds boring, but actually lots of work with ESD, etc). Combined with huge missing feature-sets in the open source tools, like extraction of designs back to SPICE circuits with parasitics and complete DRC checking, you're not going to have a fun time.

[exikyut]

Hmm, I see. Thanks for this info, and particularly the bit about the pricing.

[pjc50]

The equivalent term is "GDSII", and I think it is possible, but I'm not aware of an example. Definitely not for beginners.

"Full open source" encounters some odd corner cases in EDA because it's not software. Eg Do you use the foundry's library for things like IO pads?

[pkaye]

Transistor count impacts the size of the die which impacts yield (how many good die out of total.)