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by tonyarkles
3194 days ago
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I'd guess pin-count and driver availability. SPI has pretty well-established kernel drivers with usermode access. Using the parallel busses is either going to involve driving a ton of GPIOs or trying to map some kind of parallel peripheral into driving each screen. |
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Still, on those, it's still only 13 pins for an 8-bit parallel bus (which I think can still do 16-bit color,) rd/wr/dat-cmd/chip_en/reset, and the chip_en/reset pins are probably optional. And while they do tend to have a few hardware SPI peripherals, some of them also have flexible memory controllers which can rapidly pipeline data over a customizable interface designed for use with a variety of RAM/storage/etc banks. But I think it will probably work since TFT interfaces are essentially writing to a framebuffer. And BGA packages usually have like twice as many 'pins,' but to be fair 'real computers' do also require a lot more I/O than microcontrollers.
See [pdf]: http://www.st.com/content/ccc/resource/technical/document/ap...