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by ajross
3260 days ago
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You've lost me on what you're arguing. I'm saying "we want to spend more time integrating open hardware designs into RISC-V devices and less time making new CPU cores in our fun new HDLs". And you're saying "we can't" because... why? I know that junk is there on OpenCores too. I've looked at it. I've synthesized some of it. No one uses it on silicon. That's the part we need to fix. And it's not because of SPICE parameters being behind an NDA. There's no reason you can't plug a USB state machine into a per-process line driver, that's the way it works everywhere (even on FPGAs). Synopsys et. al. ship their verilog with the logic carefully isolated from the semiconductor process dependency (for obvious reasons). Don't tell me that open hardware device vendors can't do the same thing. They just haven't, largely because existing open source people are spending their time making CPU cores instead of integrating a SoC (and software stack) made up of open designs that can be plugged into fab-supplied analog blocks in an obvious way. |
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Why don't you quit being an arrogant armchair architect prick on Hacker News, telling everyone what they should and should not be doing, and do it yourself.
This is not an open hardware project, this is a soft CPU core intended for final use in an FPGA: that is, not intended for manufacture. The best memory controllers and GPIO on your FPGA are the ones which are burned in at the fab. Why spend precious time developing a memory controller which will ultimately underperform the one you already have as part of your FPGA? To satisfy some dood on HN?
If it's so important and you're so disappointed with the quality of published peripheral controller HDL, then surely it's your job to show us all the right way.