[BooneJS]

To be fair, BRAMs aren't reconfigurable on the fly. That is, there's no assumption of data preservation when you change them.

Processors would need to temporarily hang to reconfigure hierarchy. Execution pipelines would stop issuing and resolve all in-process instructions and push registers to a stack, the memory system would need to quiesce the memory system and flush all structures, and finally the processor could rewrite low-level addressing crossbars. Once that's done, pop the registers back into the stack and hope there's no weird interactions with any number of legacy features in any older processor architecture. :)

[nachiketkapre]

That is a great point. Yes, most of the configuration parameters for FPGA RAMs are statically configured and would need to be "reconfigured" safely. Certain parameters are dynamically controlled (can be changed during execution without reconfiguration) and do not affect data safety, like cascade control if you want to stitch together multiple RAMs on-the-fly.

[hvidgaard]

I think it can be done in a way that is quite less "stop and go". When you want to reassign a chunk, mark it as such and interrupt the core currently owning that chunk so it can do what it needs to do. Once it signal that it no longer have any data in that chuck, you simply reassign it and the new owner can start using it.