[gbrown_]

We're not likely to get below 3nm. We getting into the realm of making things on a feature set of a handful of atoms. It's insane we've got this far.

Then there's the matter of using this for production of large scale shipping chips. Note the POWER9 (IBM's next big chip) is expected to be produced on 14nm.

> we'd need a paradigm shift?

Yes we're coming to the end of the road for traditional CMOS chips. I don't think anyone really knows what's next as there's no clear successor.

I would speculate in the coming years we'll be seeing more performance coming from invocations in the data path for general purpose computing. Of course exploitation of massive parallelism will continue.

[hyperpallium]

14nm? Wait, isn't the iPhone 8's A11 to be on 10nm? I can't imagine TSMC being ahead of IBM's foundry, so what's going on here? Non-technical "nm"?

[Someone]

http://spectrum.ieee.org/semiconductors/devices/the-status-o...:

"The company’s 0.13-µm chips, which debuted in 2001, had transistor gates that were actually just 70 nm long. [...] Through all this, node name numbers continued to drift ever downward, and the density of transistors continued to double from generation to generation. But the names no longer match the size of any specific chip dimension. “The minimum dimensions are getting smaller,” Bohr says. “But I’m the first to admit that I can’t point to the one dimension that’s 32 nm or 22 nm or 14 nm. Some dimensions are smaller than the stated node name, and others are larger.”

The switch to FinFETs has made the situation even more complex. Bohr points out, for example, that Intel’s 22-nm chips, the current state of the art, have FinFET transistors with gates that are 35 nm long but fins that are just 8 nm wide."

If there wasn't such an enormous difference between the two, I bet some foundries would have silently started reporting transistor sizes in nautical miles (nm) in order to ensure the number kept decreasing.

[tormeh]

Coarser processes have their benefits, especially when they've matured for a while. When you're building a large chip you start really thinking about yield. Coarser and more mature processes give better yield.

I would assume that maximum yield would be achieved by very accurate machinery making coarse chips, like using 14nm lithography to make 22nm chips, but this is rarely done in practice, I think.