[im3w1l]

From my understanding we can't get much higher sequential instructions / second than we already have.

So the instructions have to do more each (CISC), or we have to do a lot of instructions in parallel. Maybe RISC could shine in massively parallel processing units.

[pkaye]

Although the Intel CPUs have a CISC instruction set, internally they are converted to RISC like uOPS in the early instruction decode stage. So an CISC instruction that increments a memory location is converted into uOPs to load from memory into an internal register, increment of that register followed by a store to memory. These days, the uOPS are so powerful that they do the opposite at times like merge adjacent compare and branch instruction into one uOP.

[kevin_thibedeau]

x86 has been RISC ever since the PentiumPro. The programmer visible CISC instruction set is just a compacted form analogous to ARM Thumb.