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by AWS_F1
3353 days ago
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The FPGA pins are connected to the host CPU via PCIe Gen3, 4 local DDR4 channels for each FPGA, and if you are using the f1.16xlarge, there are pins connecting between the FPGA. Both f1.2xlarge and f1.16xlarge have NVMe SSD, attached as PCIe device to the host, and not connected directly to the FPGA. One could consider using standard linux NVMe drivers or SPDK user space drivers for high throughput and low latency data movement between the NVMe SSD and the FPGA |
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