[BillBohan]

I am currently waiting for my MATRIX Voice to arrive.

https://www.indiegogo.com/projects/matrix-voice-open-source-...

I have a Spartan 3AN dev board, another Spartan6 board, and an Arty. I was using Xilinx ISE free version to develop for the other boards until I bought the Arty. It came with a one year license for Vivado. I did not know that activating the Vivado license locked me in to developing only for Arty. ISE will no longer synthesize for any other target. I strongly dislike the closed nature of their software licensing.

I am retired but the last 10 years I worked writing VHDL. I can kind of read Verilog and understand what it does but do not know it well enough to write in it. The systems I worked on were for oil well logging. My circuits went down a 16,800 ft. hole where it was 350° F and the pressure was over 7000 PSI. Production quantities were typically less than 100. We used no bigger an FPGA than was needed to keep power at a minimum as there was no way to dissipate heat. Also the circuit boards were quite small since they needed to fit into a housing less than 2" in diameter. Frequent design changes were needed but all ran on the same boards.

I am currently working on a processor design that I call NISC. The set of all opcodes is the null set. It's a single instruction machine that does a move instruction with two operands, Source Address and Destination Address. I have considered putting the specifications and design on the internet as open source but am not sure where I should put it. Would anybody be interested in seeing it and where do you think I should put it?

[mch82]

Check out the Open Source Hardware Association best practices document for some ideas of what people release: https://www.oshwa.org/sharing-best-practices/

BeagleBone Blue is a good recent example of an open hardware project using GitHub: https://github.com/beagleboard/beaglebone-blue

OpenROV is another example: https://github.com/OpenROV

[CamperBob2]

I did not know that activating the Vivado license locked me in to developing only for Arty. ISE will no longer synthesize for any other target. I strongly dislike the closed nature of their software licensing.

That is absolutely not correct. Something else is going wrong with your licensing. Have you asked around on the Xilinx customer forum?

[amelius]

Curious, how would one implement adding two numbers on your NISC architecture?

Or is the idea that you move the operands to the inputs of an adder circuit, and then move the result?

How would conditional control flow work?

[bitexploder]

https://recon.cx/2015/slides/recon2015-14-christopher-domas-...

Movfuscator

[BillBohan]

Thanks for this link. I will read it when I have time.

I currently have an accumulator at an address.

Moving to the next address ANDs with the accumulator.

Moving to the following address ORs with the accumulator.

Subsequent addresses XOR, ADD, ADC, SUB, SBB with the accumulator.

I have a location called Z and one called NZ which may be written. Reading from either location returns what was written to Z if the Z flag is set, otherwise both read what was written to NZ. Moving either to the PC effects a conditional JUMP. Moving either to the relative register adds it to the PC (relative conditional Jump). Moving either to the Indirect register pushes the PC on the stack and writes to the PC (conditional call).

I envision the capability of using the accumulator as a floating point register and having locations which perform floating point operations in a similar manner. It could also be considered as a vector and there could be locations which perform vector operations on it.

[rjsw]

I would have expected your Vivado and ISE licences to be separate, do you still have contacts with a FAE to ask for help ?

[alnitak]

Do it on Github!

[BillBohan]

OK

https://github.com/BillBohan/NISC

[alnitak]

Out of curiosity, what is the advantage of having a single instruction?

I imagine that the benefit of a simple syntax in the assembly code is counterbalanced by the complexity of implementing complex logic, say control flows?

Also, what is the performance impact of this approach? Wouldn't it cause more cycles for the same code in general, compared to multiple instructions?

Lastly, could there be an optimized hardware for this set? (Executing directly on the RAM chipset maybe?) How do you see it perform against more traditional hardware?

[BillBohan]

I see one of the advantages being that it is very easy to learn due to its simplicity. There is also no need for complex instruction decoding placed on the hardware designer.

For software there may be a slight increase in complexity for control flow because it is necessary to specify the addresses where execution continues both when the condition is met and when it fails versus CISC which specifies only the address to branch to when the condition is met and defaults to the next instruction inline when it fails but there is also a gain in flexibility by specifying both addresses because you could, for example, call one subroutine for Z and call another subroutine for NZ and both would return to the next instruction inline.

When I first read about Move machines it appeared that they were very inefficient and the simple ones described were. In the decades since then I have devised means to offset that inefficiency with more powerful hardware functions. Especially with an FPGA target it is possible to perform complex functions in hardware that only needs to be memory mapped. Depending on your application you could have vector math, complex number math, or SIMD instructions which run in a single machine cycle. It is possible to have a shift-and-add multiplier which takes several cycles that can be loaded then you could perform some other operations while waiting for completion. I have written shift-and-add multiply routines for microprocessors which needed the processor to do the shifts and to do the adds which kept it fully occupied. While I do not claim that the design I have documented is the optimal processor, I maintain that it should have reasonable performance.

One of my goals in releasing this design is to draw interest and receive suggestions and recommendations for improving it from the highly intelligent community that reads HN and uses Github. I would like to see it optimized.