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by blasdel 5861 days ago
Avoid ever referring to it as code. There'll be a few cases where it's valid nomenclature, but most of the time it gets you headed in the wrong direction.

The trick would be a synthesis that preserves line-number metadata, and then a linting place-and-route that just creates idealized graphs and lets you see where your design is exploding or clocked funny or whatever.
1 comments
gte910h 5860 days ago
>Avoid ever referring to it as code

I tend to call verilog or VHDL "VHDL Hardware Specification". Try to make it sound as un codelike as possible

After all VHDL was the way that military contractors came up with to specify their parts to the Govt in case they went belly up.

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harnhua 5859 days ago
As I was trained in Verilog and know little about VHDL, to be honest, I'm not quite sure why "code" is inappropriate.

But thinking about your(blasdel's and gte910h's) comments, I'm beginning to see how error-checking can and should be different for FPGA development.

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blasdel 5859 days ago
Because neither Verilog nor VHDL is code. HDL is a slightly handwavey description of the graph of a machine, not something that runs on a machine.

You have wires, not variables: real physical wires connecting gates and LUTs. Since you're dealing with real-world electrical current, each wire can be in one of four binary states (null, low, high, grey). There's no concept of time beyond the speed of light itself unless you deliberately bind a clock line from the outside to a wire.

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