[Coding_Cat]

With how big these chips are getting, I wonder if the next iteration will have an HBM last-level cache on chip.

[phkahler]

That's the old EHP concept.

http://wccftech.com/amd-exascale-heterogeneous-processor-ehp...

I'd like to have that in the old project quantum package: http://wccftech.com/amd-project-quantum-not-dead-zen-cpu-veg...

That would be a TFLOPS level supercomputer on your desk.

[keth]

Here is the newest PDF about something like that: http://www.computermachines.org/joe/publications/pdfs/hpca20...

[throwawayish]

"IBM did it first"

Well not with HBM (which is DRAM), but huge amounts of L3 SRAM on a MCM... POWER5 I believe.