[dooferlad]

A NOP shouldn't ever take up actual pipeline space in a modern CPU - it can be discarded at decode.

A clock is a signal that is used as a valid signal for the data moving across a bus. That could be as short as between pipeline stages.

With async you have a different valid signal, which you will need to derive.

With aggressive dynamic frequency and voltage scaling, clock gating, power gating and having different power and clock islands you get a design that is very difficult to improve on. What AMD has done recently with circuits that lower voltage based on reading the environment on chip rather than sticking to a frequency: voltage mapping is a nice optimisation.

What async designs don't improve on are all the static power issues that are increasingly important.

It all adds up to being an interesting take on the problem of digital design, but not much more.