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by Cyph0n 3409 days ago
Intel's FDIV bug was an outlier. Besides, nowadays most of the ISA is implemented in microcode[1]. There are two advantages to this approach: 1) it is much easier to verify the microcode unit (it's simpler/smaller), and 2) it allows CPU vendors to "fix" ISA implementation issues post-release by issuing microcode updates.

[1]: ISA => microcode is equivalent in some respects to C => LLVM IR
2 comments
mtanski 3409 days ago
Outlier? I would say uncommon but not an outlier. Here's a non-exhaustive list. http://wiki.osdev.org/CPU_Bugs

There was also an issue with transaction memory with both Haswel & Broadwell. The fix was to disable TSX support via micro code update. I wouldn't call disabling a fix personally. I doubt Intel even compensated the folks who bought it for the TSX support.

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puzzle 3409 days ago
Yeah, that list is far from exhaustive. Years and years ago, Google's websearch cluster validation suite found a tricky bug that isn't on that list. The exchange with the CPU manufacturer was amusing.
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Cyph0n 3409 days ago
Given how many Intel/AMD/etc. CPU releases there have been, I would still refer to such glaring implementation bugs as outliers.
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bonzini 3409 days ago
Most of the ISA may be implemented in microcode, but the parts that matter are certainly not microcoded!

For example the TLB access and the fast path of the TLB miss are not microcoded. You only get to microcode if you have to set an accessed bit or a dirty bit, or if there is a page fault.

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