[gluggymug]

You've pretty much hit the nail on the head. What people outside of the EDA field fail to understand is they are coding at a much higher level. RTL does not model all the aspects of the logic. You have different signal delays due to lots of different reasons: fanout, wire lengths etc. As you go through different stages of synthesis via these tools, a lot of decisions are made governed by the constraints files. Each decision affects the performance of the design. It's slow because it's doing a lot of work to optimize speed or area. Some designs won't fit the constraints. Then it reports errors.

The tools are trying to help. The end product is the physical device. The various models are all just abstractions of the physical device. The tools are reporting the problems on the abstractions to assist you to improve the physical device. If you can understand the reports, you can improve things, either altering the RTL or adding more constraints.

The point being that the only time RTL is actually run like a software program is during simulation. This simulation is only an approximation of how the actual thing will work. It is not like SW. The tools do a lot of other things with that RTL. Maybe if people don't throw garbage in, it wont crap itself trying to figure it all out.