|
|
|
|
|
|
by masklinn
3434 days ago
|
|
|
Rust has Tier 2 support[0] for ARMv6 to ARMv8 and Tier 3 support[1], so there are experimental limited[2] backends for the various Cortex in Tier 3. However the ESP8266 is built around Tensilica's Xtensa, not ARM's Cortex. There currently is no support whatsoever for Xtensa in LLVM (let alone in Rust). Current microcontroller work is on MSP430[3] with work being planned for Amtel AVR[4] since the AVR branch was merged into LLVM in November 2016. Xtensa is quite literally nowhere[5]. [0] guaranteed to build & binaries provided but tests are not automatically run [1] supported in the codebase but no guarantees that it even builds [2] only Core, no standard library [3] https://github.com/rust-embedded/rfcs/issues/20 [4] https://github.com/rust-embedded/rfcs/issues/3 [5] https://github.com/rust-embedded/rfcs/issues/2 |
|
|
DOH!
I have to say, though, that having the AVR code generator merged is very cool. At one time I was a big user of avr-gcc and remember when the AVR LLVM effort was just getting started. I haven't been following it, though.
One of the annoyances with gcc is that the optimizer kept wanting to use code motion to relocate the interrupt disable instruction to the beginning of the function it was found in. The only way to keep the optimizer from doing that would have been to make the instruction depend on all of RAM, which would effectively disable optimization for any function that disabled interrupts. So coding critical sections required a bit of jiggery-pokery to keep the optimizer from breaking your code. I hope the LLVM back-end found a way around that.