[gluggymug]

"We've already seen this happening on the HDL side of things; open-source, research-driven efforts like Clash and Chisel are orders of magnitude better than the crap that industry has been using for years (VHDL and (System) Verilog). "

As someone in the industry, I would have to disagree. I question this every time someone claims it's so awesome. None of those solutions can run simulations on the back annotated netlist . How do you design without a simulation tool that can work at every stage of the design flow?

RTL is a behavioral model. Post synthesis is the physical model. What do you think synthesis engineers do? Just sit around watching the tools run?

[kmicklas]

> What do you think synthesis engineers do? Just sit around watching the tools run?

Can you explain briefly for someone not in the industry why it's not that simple? This seems like it should be a 100% automatable process.

[gluggymug]

Things don't just work automatically. Some idiot can throw a design in that doesn't just synthesize.

After synthesis, your RTL becomes a gate level representation. You then place your logic i.e. Your memory logic near your memories, I/O logic near your pins etc. You then make clock trees for your various clocks. You don't want related logic clocked by different parts of the clock tree. Once you have stuff physically located, you back annotate and do your static timing analysis.

You generally run simulation on the different stages of synthesis. Someone has to debug all these simulations. They never just pass.

There is a big difference between RTL and gate level simulation. A test passing in RTL is only the 1st stage. RTL doesn't have any wire models so no delays are in there. Gate level sims can run with delays in there.

Synthesis tools can also tell you it doesn't pass timing through static timing analysis but asynchronous parts of the design can't be analyzed. You need simulation there!

[zerohp]

Fully automatic tool flows give lower quality results than tools+trained engineers. Most of the problems are NP-Hard. It's an active area of research.