[e19293001]

I was interested to be an active contributor for open-v but this project turned out to be like a school project. Tried to clone the mriscvcore and created my own testbench for the code then found out to have a simple critical bug on the handshake signals for read and write ports[0]. I don't know what is really happening to the authors but they seem to be inactive for a long time which is so disappointing.

I am still searching for an active RISC-V verilog implementation project for me to contribute through design and verification. For those who are looking for contributors you may want to drop me an email: my username at gmail dot com.

[0] - https://github.com/onchipuis/mriscvcore/issues/3

[aseipp]

Why not picorv32? Size-optimized, open licensed (no 64-bit, but that's where you could come in and be a star!) Clifford Wolf, the author, also wrote Yosys and Icestorm, which you can use to synthesize picorv32 for the iCE40 FPGAs with a fully open source HDL toolchain. It's really nice and usable!

Clifford has also been doing a lot of cool work adding SMT-based verification tech for synthesis via Yosys, and even started working on a verification bench for RISC-V implementations: https://github.com/cliffordwolf/riscv-formal - he's also very nice and approachable IMO. I'm sure he'd appreciate some extra help.

Sounds like exactly what you want, perhaps.

[xkarga00]

You may want to check out lowRISC.

http://www.lowrisc.org/

https://github.com/lowRISC