[jwise0]

Well, what you want and the physical realities of synthesis are different :-)

In the early days of compilers, of course, you were mostly writing C as a macro language for your system's assembly language. If you wanted your program to perform well, you'd have to write C that was, more or less, a translation of assembly that you'd constructed in your head first. If you wrote bizarre C, you'd either get incorrect results, or if you were lucky, you'd get correct but inefficient results.

But that's also Dan's point: Verilog isn't a "high level language". You don't write programs with it, you describe hardware with it. (In fact, that is why it is called a 'hardware description language'!) So if you try to write a program, instead of describing hardware, you'll get something that isn't really either.

[marcosdumay]

> Well, what you want and the physical realities of synthesis are different :-)

Then why doesn't the language let me describe what I want, and if reality disagrees, throws some compiling errors back?

Our current HDLs are lower level than block diagrams. And anything higher level they may claim to provide is iffy and won't work on practice. That's not a problem with the languages, but it is a problem for hardware development.

[raverbashing]

> If you wanted your program to perform well, you'd have to write C that was, more or less, a translation of assembly that you'd constructed in your head first.

Maybe in really old compilers

> You don't write programs with it, you describe hardware with it

Which is fair enough, but it seems the "hardware description" pretends to be of a higher-level than it really is.

If you need the user to describe gates and flip-flops and how they connect then make them describe this.

[vvanders]

> If you need the user to describe gates and flip-flops and how they connect then make them describe this.

You're talking about RTL, which is exactly what these languages output.

Fundamentally they're not programming languages, unfortunately the initial instinct is to treat them as such and it leads to a ton of confusion.

[raverbashing]

> You're talking about RTL, which is exactly what these languages output.

So why am I wasting time with verilog then if I have to "design" in low-level then translate it to verilog?

[wolfgke]

> You're talking about RTL, which is exactly what these languages output.

If VHDL/Verilog would output RTL, you could easily analyze it just as you analyze assembly output of your favorite compiler. Unluckily the output is some proprietary bitstream for the FPGA.

[k0ngo]

Just as a software compilation flow is devided into preprocessing, compilation, assembly, and linking, a HDL flow is divided into synthesis, mapping, place and route, timing analysis and bitstream generation. RTL is the output of the synthesis stage and is readily available to the designer, typically both as code and as a graphical schematic.

[vvanders]

It's been a while since I poked around in RTL but last time I was working with FPGAs it was possible to inspect RTL and view the synthesis results.

[pklausler]

> In the early days of compilers, of course, you were mostly writing C as a macro language

In the early days of compilers, we were mostly writing FORTRAN.