[bisrig]

To add to this - a lot (maybe all?) of the functionality that is described by the concept of "overlays" maps to the design and implementation of the programmable logic in a coprocessor system. To use Xilinx terms, this would be the block diagram that describes the periphery that connects to either a soft- or dedicated-core processor. The block diagram will control the usage of programmable logic cores and provide hooks for the BSP generator and SDK to wrap these in ways useful for software development - memory maps & base addresses, associated drivers, etc.

The big value add that I see here is that the management of these overlays has traditionally been painful, especially when trying to swap overlays at runtime - this is always sold as one of the big benefits of SoC processor+FPGA, that you can do things like dynamic hardware accelerators based on what software is currently running, but more than some assembly has always been required. This seems like a nice step in the direction of having reasonable mechanisms to reconfigure based on application.

[ZenoArrow]

I could be wrong, but I'd imagine the overlay functionality is fairly similar to 'header' files in other programming libraries, in that they're a list of instructions available to program with, that point to a precompiled library (in this case, hardware-accelerated libraries).