|
|
|
|
|
|
by FullyFunctional
3545 days ago
|
|
|
The third trade off is cycle time; the larger the memory, the longer it takes to access it. This is why L1 caches are typically 16-64 KiB and despite that access is typically 2-3 cycles. However, 3+ cycles is difficult to hide in an in-order processor like this. |
|
|