[nickpsecurity]

There was also problem where the speedup might have happen with classical computing. They were comparing their algorithm for their architecture against a single CPU implementation done same way in one paper. I've seen FPGA's get 3 digit speedups on problems they could brute force when redone for their architecture. Something the size and cost of D-Wave machine could easily use something like FPGA's, ASIC's, and/or NUMA links. I'm not sure it would achieve the exact results but I'd like it ruled out that they didn't build a MPP of ASIC's for the specific problem.