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by trsohmers 3592 days ago
EEPROMs are mostly only used for CPLDs (very cheap very very small FPGAs)... "Big" FPGAs as used here use SRAM, and are rated to be reprogrammed 100s of thousands of times, but should last for millions. I have reprogrammed my Xilinx and Altera FPGAs hundreds of times over a course of a couple of days ;)

EDIT: I should note that in the case of using SRAM, the device would only be programmed as long as the device is powered on. You would use EEPROM even on large FPGAs if you have the same design to be flashed to the FPGA between reboots. I personally never use EEPROM for storing the design as I have my FPGAs constantly connected to a computer for programming. My main point is that the FPGA can be programmed a functionally infinite number of times, though if you want the design to remain through reboots through an external memory, the limitation is that external memory, not the FPGA itself.
1 comments
nickpsecurity 3592 days ago
Are you able to simulate your Rex chip on one FPGA, do you just do a piece at a time, or over several? And what kind of FPGA's? Curious what hardware it takes to support developing something like that.
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trsohmers 3592 days ago
We do most stuff on a single FPGA... Our development flow is parameterized in a way so we can generate RTL with different numbers of tiles, SRAM per tile, and many other details within seconds of an RTL change. We have an Achronix Speedster that can fit 16 of our cores on it (our full test chip), while our cheaper Xilinx Kintex Ultrascale boards can comfortably fit 8 but can do 16 if we cut the SRAM size down from what we have in the real chip. You could split designs across FPGAs (The Dini Group sells systems using Xilinx and Altera chips built for this), but I have heard it is a real PITA, and we're doing fine with what we have right now.

I'd love to get a real ASIC simulation/emulation platform like Synopsys's Zebu or HAPS... Both use multiple Xilinx FPGAs linked together and easily integrate with the Synopsys EDA flow. Cadence also has the Palladium emulation platform, but those boxes approach the cost of a house in the Bay Area.

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nickpsecurity 3592 days ago
"We have an Achronix Speedster"

My favorite!

"Both use multiple Xilinx FPGAs linked together and easily integrate with the Synopsys EDA flow. Cadence also has the Palladium emulation platform, but those boxes approach the cost of a house in the Bay Area."

Sounds like a business opportunity for someone. I know it could be cheaper and still profitable.

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