[seldridge]

The really cool thing is that existing implementations of RISC-V microprocessors, like what Berkeley provides, rocket (https://github.com/ucb-bar/rocket) and boom (https://github.com/ucb-bar/riscv-boom), and lowRISC uses and modifies have a dedicated accelerator socket.

We've have good luck developing software/hardware infrastructure for machine learning accelerators and interfacing an example multilayer perceptron backend with this infrastructure (with Linux integration ongoing). This work (shameless plug: https://github.com/bu-icsg/xfiles-dana) may provide a starting point, examples, or general guidance for developing machine learning or other accelerators in this space.

But, I can't overemphasize how the ongoing work at Berkeley and lowRISC have facilitated this process.