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by _-__--- 3670 days ago
Here's some spec on the chip itself (KnuEdge seems to be a larger holdings company of sorts, the chip is more associated with subsidiary KNUPATH):

https://www.knupath.com/products/hermosa-processors/

2 comments

Very interesting.

It's still quite vague but this seems like a better summary: "We combine distributed computing cores with an ultra-low latency fabric in a massive-bandwidth “push” model, which delivers higher performance from small to ultra-large deployments."

Basically, it seems like the chip is aiming to provide more memory bandwidth for parallel computing, more relative to GPGPU computation, which indeed provide a lot of parallel computation but has a somewhat limited memory bandwidth.

The "neural" part seems to be just emulating some aspect of neural network architecture for the memory architecture and the chips seem to be suited for general purpose parallel computation (indeed, apparently aiming to be better suited than existing chips).

And I think it's good that the chips apparently aren't like IBMs "brain on a chip" project, which as far as I can tell is a complete mistake; given that's just emulating one neural network architecture, it prematurely commits to that approach when the proper nn architecture is still a question in considerable flux.

I hope this is something that could compete with Google's Tensor Flow chips and even be more general-purpose. If it is, that would be a great thing.

i do wonder what the ARM license is being used for - acting as an interface to the cores themselves?
Looks like an FPGA with only the DSPs and no logic units.

The SoC is probably used in the same way (high level tasks like networking etc.) as it is in FPGA land.

Agreed. I've seen a few similar mockups that used a processor IP as the chip-level "traffic cop".