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by amelius 3696 days ago
Does it do pipelining, branch prediction and (hyper)threading? How is its memory hierarchy (cache levels) organized? Does it support a privileged mode? Does it support hardware page faults? Did you implement floating-point operations?

> In order to be able to program it at all, I wrote a very simple compiler (strictly speaking it’s actually an assembler)

Does that compiler/assembler run on your hardware?

2 comments

In a word: no. Processors this simple don't implement any of the features you mention, including multi-level memory hierarchies, and I doubt the author had any inclination to make the assembler self-hosting.
I'm not saying one should expect or demand it in a project like this, but minimalistic pipelining should be doable; both the 6502 (http://www.6502.org/users/andre/65k/arch.html#pipelining) and (IIRC) the 8080 started fetching the next instruction before finishing execution of the current one, where possible.
Do you have an example of a case where this provided a performance benefit to 6502 code?
Why should it?