Hacker News new | ask | show | jobs
by frozenport 3738 days ago
Actually Verilog developers are orders of magnitude more efficient than their VHDL counterparts.

http://www.bawankule.com/verilogcenter/contest.html

1 comments

Wow 1997, but thanks for the link, it was a fun read. It'd be fun to hear from people in the industry what their experience has been on larger multi-people projects -- e.g. how long would it take to create an ASIC like http://www.jandecaluwe.com/hdldesign/digmac.html ?