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by sklogic
3736 days ago
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> If it's Python, it's not a DSL by definition. Scala is not any better. It's exactly the same kind of a eDSL - no macros, nothing, just generating objects in runtime and then serialising this tree into a Verilog code. Nothing fancy. > around state machines What state machines?!? It does not have any more features for defining FSMs than an underlying Verilog. |
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