[nickpsecurity]

Someone please tell these people about Archipelago FPGA:

http://www.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-43...

It's already at 45-65nm with configurable logic and memory cells. They're working on multipliers next. Open-source flows for bitstream and synthesis already exist that can be targeted to this if it hasn't already. Lean on those people for something to use and you might get it. Write other students working in FPGA-related fields to contribute their prototype enhancements to Archipelago and all get published. We'll get stuff over time that commercial or grant-based efforts can turn into a real chip.

[Andrey_Filippov]

Thank you, at leas one of "these people" got it. Interesting project, but again - it is still far performance-wise. We really appreciate work of developers of the Free Software toolchain, but we work in a slightly different area as we need much larger devices. Yes, we use proprietary tools (with some limitations described in the original post). These tools are physically isolated from my workstation - they are held a "jail" - a separate Linux box controlled from the IDE on a Free Software -only workstation. Icarus/GtkWave are launched locally, but ISE/Vivado(tcl console)/Quartus - over ssh+rsync.

[nickpsecurity]

"but we work in a slightly different area as we need much larger devices"

Doing analog design at a deep submicron node is very hard and expensive. Unlikely to be open-sourced. That's why I encouraged you to find academics developing digital cell libraries or open-source FPGA's to tell them what you need. They might develop it for you as part of their academic work.

"These tools are physically isolated from my workstation - they are held a "jail" - a separate Linux box controlled from the IDE on a Free Software -only workstation. Icarus/GtkWave are launched locally, but ISE/Vivado(tcl console)/Quartus - over ssh+rsync."

Good that you're making an attempt. Must remember threat model, though: hackers hitting box from firmware to OS to software to audio/wireless devices onboard; subversion of EDA tooling lets them active trap door with simple command or hide exploit in an update; physical theft of the box. You need mitigation for each of them.

A separate box is always best. Use write-only media for backups of source and for updates to EDA software if possible. The box distributes its software either via a data diode for one-way transmission or a CD burner. Full-disk encryption to mitigate theft optionally with tamper-resistant marking on PC and inspections for keyloggers/implants. That you use OSS simulation after proprietary tooling is smart and my exact recommendation. ;)

Btw, check out Qflow as there's not enough projects testing it and providing Cliff feedback:

http://opencircuitdesign.com/qflow/

[ashitlerferad]

Here is the github for that:

https://github.com/haojunliu/OpenFPGA